As techniques that have examined by the present inventors, for example, there are the following techniques in a semiconductor integrated circuit device mounted with a time sharing virtual multi port memory or the like.
A technique described in Japanese Patent Application Laid-Open Publication No. 8-212784 (Patent Document 1) is that by controlling an internal portion of the memory in a time sharing virtual multi port memory using memory cells with a small area by clocks which is the same frequency with that of an external portion thereof, an external clock time can be made shorter than an access time. The time sharing virtual multi port memory is realized by a constitution including a latch circuit, an internal memory, a multiplexer circuit, a circuit to allocate data, and a PLL circuit. The multiplexer circuit and the circuit to allocate data, the internal memory, and the latch circuit are controlled by a clock signal that is generated by the PLL circuit and is higher in frequency than the external clock, and data corresponding to plural ports is processed in a time sharing manner.
A technique described in Japanese Patent Application Laid-Open Publication No. 2005-85344 (Patent Document 2) is that, in a configuration including a memory core provided with a port allowing input/output of a signal and a port extending circuit that is connected to the memory core and can extend a port of the memory core by time sharing, by providing a port switching circuit that can perform switching a port realized by time sharing, a layout of a semiconductor storage device is standardized, regardless of the number of ports or a port function, a setting of a port realized by time sharing according to a user specification is made possible and cost reduction of a multi port RAM in a time sharing system is achieved. An internal clock for controlling an operation timing of an internal memory is generated by a delay device that can set a pulse width.